An n-channel metal-oxide semiconductor (“NMOS”) transistor includes a drain, source and gate. When an NMOS transistor is used as a switch, the on/off state of the transistor is determined by the voltage difference between the NMOS gate and either the drain or source. An NMOS transistor is switched “on” if the gate voltage Vg is greater than either the drain voltage Vd or source voltage Vs by at least a threshold voltage Vt. Thus, control voltages applied to an NMOS transistor should be at least equal to the transistor's threshold voltage Vt plus the maximum voltage applied or potentially applied to either the drain or source.
In a conventional five-transistor CMOS image sensor pixel 100 with dual conversion gain, as illustrated in FIG. 1, NMOS transistor gate control voltages need be at least one threshold voltage Vt higher than a supply voltage Vaapix to ensure that the transistors are turned on. The transistors in pixel 100 include a transfer transistor 110, a reset transistor 120, a source follower transistor 130, a row select transistor 140 and a dual conversion gain transistor 150. The transfer transistor 110, when made operative using a transfer control signal TX with activating voltage Vtx, transfers charge collected by a photodiode 112 to a floating diffusion region FD. The reset transistor 120, when made operative using a reset control signal RST with activating voltage Vrst, resets the floating diffusion region FD to the supply voltage Vaapix. The source follower transistor 130 has its gate connected to the floating diffusion region FD and is connected between the supply voltage Vaapix and the row select transistor 140. The source follower transistor 130 converts the potential at the floating diffusion region FD (associated with the transferred charge or reset voltage) into an electrical output voltage signal Vout. The row select transistor 140 is controllable by a row select signal RS with activating voltage Vrs for selectively connecting the source follower transistor 130 and the output voltage signal Vout to a column line of a pixel array. The dual conversion gain transistor 150 has its source terminal connected to the floating diffusion region FD and its drain connected to a first side of an in-pixel capacitor C1. The gate of the dual conversion gain transistor 150 is connected to a dual conversion gain control signal DCG with activating voltage Vdcg. The second side of the capacitor C1 is connected to a ground potential. The capacitance of the capacitor C1 is coupled to the floating diffusion region FD when the dual conversion gain control signal DCG is applied to turn on the dual conversion gain transistor 150. Once the capacitor C1 is coupled to the floating diffusion region FD, the conversion gain of the floating diffusion region FD will decrease. Thus, the floating diffusion region FD has a second conversion gain when the dual conversion gain signal DCG turns on the dual conversion gain transistor 150. As such, the dual conversion gain transistor 150 and capacitor C1 form a conversion gain altering circuit for the floating diffusion region FD.
In the pixel 100, the maximum drain or source voltage for the transfer transistor 110, reset transistor 120, row select transistor 140 and the dual conversion gain transistor 150 is equal to the pixel supply voltage Vaapix. Therefore, the control signal activating voltages Vtx, Vrst, Vrs and Vdcg should be at least equal to the pixel supply voltage Vaapix plus a threshold voltage Vt.
Unfortunately, the threshold voltage Vt of an NMOS transistor is dependent on the individual characteristics of a transistor as well as the drain or source voltage. Thus, in the case of the transistors in pixel 100, the threshold voltage Vt for a specific transistor is dependent upon physical characteristics of the transistor and the maximum voltage supplied to the terminals of the given transistor. In FIG. 1, the maximum voltage supplied to the terminals of any of the transistors in FIG. 1 is, generally, the supply voltage Vaapix. Typically, the supply voltage Vaapix in pixel 100 is rated to have a ±10% tolerance. If, for example, the supply voltage Vaapix is rated to be 3.3V±10%, it is possible that the maximum voltage applied to a transistor source or drain is 3.6V. This means that the control voltages Vtx, Vrst, Vrs and Vdcg should each be at least 3.6V plus the threshold voltage Vt that corresponds to a source or drain voltage of 3.6V (which is, incidentally, higher than the threshold voltage Vt that corresponds to a source or drain voltage of 3.3V). Unfortunately, determining the threshold voltage Vt is complicated by the body effect of the transistors caused by their positional location in a circuit, as explained in greater detail below.
Because the required control voltages vary, one method of providing control voltages is to assume a constant threshold voltage Vt of sufficient value in order to guarantee a sufficient gate control voltage. For example, a control voltage for the transistors in pixel 100 could be made equal to the supply voltage Vaapix plus a threshold voltage Vt that is large enough to always correspond to the maximum source or drain voltage (e.g., 3.08V in the case of a rated supply voltage Vaapix of 2.8V±10%). Though this approach may be adequate for some pixel designs utilizing a lower supply voltage of 2.8V or less, it can be problematic for the pixel 100 when the supply voltage Vaapix is higher than 2.8V (e.g., 3.3V), as higher supply voltages result in applied control voltages approaching the maximum rated operational range of the transistors. By repeatedly applying unnecessarily high control voltages to the gates of NMOS transistors, hot carrier degradation of the transistors occurs and the lifetime of an image sensor using a pixel having such transistors is reduced. In other words, it is preferable to set control voltages no higher than necessary. Although the problem has been explained using, as an example, a five transistor pixel having an adjustable conversion gain, it should be evident that the problem exists in other pixel circuit designs employing NMOS transistors, as well as in other circuits using NMOS transistors.